Job Description

• Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

• Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experience
• Strong understanding in the RTL2GDSII flow and design tapeouts in 16nm/14nm or below process technologies
• Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
• Experience working with most EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre.

• Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
• Experience in Block-level and Full-chip floor-planning, power grid planning
• Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
• Experience with Python, TCL, Perl programming.

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